Customizable ramp-up and ramp-down amplitude profiles for a digital power amplifier (dpa) based transmitter

ABSTRACT

Apparatuses, systems, and methods for a digital power amplifier (DPA) to generate a monotonic and linear ramp-up and ramp-down for a time division multiple access (TDMA) slot transmission are described. In one aspect, a monotonic and linear amplitude-to-control input code relationship model is generated for the DPA and stored. When the DPA needs to generate a ramp-up or ramp-down, the stored monotonic and linear amplitude-to-control input code relationship model is used to shape the input control code before it is input into the DPA. A new monotonic and linear amplitude-to-control input code relationship model may be generated and stored if the operating conditions change. The apparatuses, systems, and methods described herein may be applied to a multi-standard broadband modem chip capable of 2G transmission.

PRIORITY

This application claims priority under 35 U.S.C. §119(e) to a U.S.Provisional Patent Application filed on Feb. 3, 2016 in the UnitedStates Patent and Trademark Office and assigned Ser. No. 62/290,833, theentire contents of which are incorporated herein by reference.

FIELD

The present disclosure relates generally to digital power amplifier(DPA) based transmitters, and more particularly, to providingadaptive/customizable ramp-up and ramp-down amplitude profiles for aDPA-based transmitter.

BACKGROUND

While the technology for cellular communication is constantly evolving,with network providers pushing the 3G/4G technologies into the market,legacy 2G technologies still account for a major portion of total mobilebroadband connections, and subsequently cellular handsets have tosupport 2G, 3G, and 4G modes of communications. Developing such amulti-standard mobile terminal demands a broadband modem chip with thehighest possible levels of integration within a minimum silicon area,which can be difficult and costly.

One reason for the difficulty is that the electrical and systemrequirements specifications of the 2G, 3G, and 4G standards aresignificantly different. The 2G standard uses a time division multipleaccess (TDMA) system in which the mobile terminal's transceiver operatesin burst mode (i.e., quickly turning on and then off) so it can transmitin its allocated time slot in a subframe of eight slots. See, e.g.,European Telecommunications Standards Institute (ETSI) Global System forMobile Communications (GSM) 05.05 ver. 8.5.1 Release 1999: “Digitalcellular telecommunications system (Phase 2+); Radio transmission andreception” (EN 300 910 V8.5.1 (2000-11)) (hereinafter “ETSI GSM Release1999” will refer collectively to the documents forming ETSI GSM Release1999); online athttp://www.etsi.org/deliver/etsi_en/300900_300999/300910/08.05.01_60/en_300910v080501p.pdf,which is hereby incorporated by reference in its entirety. Otherstandards, such as 3G and 4G, use, for example, frequency divisionmultiple access (FDMA), orthogonal FDMA (OFDMA), and spatial diversity(such as, e.g., multiple input multiple output (MIMO)), as well as TDMA.

In legacy 2G handsets, a dedicated 2G-PA front-end module withpower-ramp control was used to guarantee these conditions and more.However, such a dedicated 2G-PA is too expensive to implement in amultiple standard mobile terminal, e.g., a mobile terminal that has thecapability to transmit and receive 2G, 3G, and 4G standard signals.

SUMMARY

Accordingly, the present disclosure has been made to address at leastthe problems and/or disadvantages described above and to provide atleast the advantages described below.

According to an aspect of the present disclosure, a method is provided,including: detecting one or more control input codes to a digital poweramplifier (DPA) that generate a non-monotonic amplitude output;generating a monotonic amplitude-to-control input code relationshipmodel for the DPA based on the one or more control input codes;adjusting the monotonic amplitude-to-control input code relationshipmodel to construct a monotonic and linear amplitude-to-control inputcode relationship model; and storing the monotonic and linearamplitude-to-control input code relationship model, wherein, during rampgeneration by the DPA, the stored monotonic and linearamplitude-to-control input code relationship model is applied to acontrol code for one of a ramp-up and a ramp-down before the controlinput code is input to the DPA.

According to another aspect of the present disclosure, a method isprovided, including: if a time division multiple access (TDMA) slot isto be generated by a digital power amplifier (DPA), retrieving controlinput code for a ramp-up shape from a ramp shape storage, where thecontrol input code is for controlling an amplitude of the DPA; adjustingthe retrieved control input code for frequency and amplitude; shapingthe frequency-adjusted and amplitude-adjusted control input code basedon a monotonic and linear amplitude-to-control input code relationshipmodel; and inputting the shaped control input code to the DPA togenerate the ramp-up shape, wherein the monotonic and linearamplitude-to-control input code relationship model is based on anamplitude-to-control input code relationship of the DPA.

According to yet another aspect of the present disclosure, a broadbandmodem chip is provided, including: a digital power amplifier (DPA); atleast one non-transitory computer-readable medium; and a processor,wherein, if a time division multiple access (TDMA) slot is to begenerated, the processor executes instructions stored on the at leastone non-transitory computer-readable medium, which, when executed, hasthe broadband modem chip perform at least the following steps:retrieving control input code for a ramp-up shape from a ramp shapestorage, where the control input code is for controlling an amplitude ofthe DPA; adjusting the retrieved control input code for frequency andamplitude; shaping the frequency-adjusted and amplitude-adjusted controlinput code based on a monotonic and linear amplitude-to-control inputcode relationship model; and inputting the shaped control input code tothe DPA to generate the ramp-up shape, wherein the monotonic and linearamplitude-to-control input code relationship model is based on anamplitude-to-control input code relationship of the DPA, and waspreviously generated and stored.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certainembodiments of the present disclosure will be more apparent from thefollowing detailed description, taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a diagram showing different aspects of a 2G slot transmission;

FIG. 2A is a block diagram of a Digital Power Amplifier (DPA) to whichembodiments of the present disclosure can be applied;

FIG. 2B is a graph of output amplitude vs. DPA control code that ismonotonic and linear;

FIG. 2C is a graph of output amplitude vs. DPA control code that isnon-monotonic and non-linear;

FIG. 3 is a flowchart of the general operations for amplitude-to-controlinput code relationship model creation and ramp-up/ramp-down generationfor a DPA according to an embodiment of the present disclosure;

FIG. 4 is a block diagram of a DPA with a ramp generation blockaccording to an embodiment of the present disclosure;

FIGS. 5A-5C are amplitude graphs illustrating examples of how the rampshape is manipulated in a ramp generation block according in to anembodiment of the present disclosure;

FIG. 6 is a flowchart of the real-time operation of a ramp generationblock according to an embodiment of the present disclosure;

FIG. 7 is a flowchart of the one-time operation for generating arelationship model to be used by a ramp generation block according to anembodiment of the present disclosure;

FIG. 8A is a graphic illustrating an example of mapping input codes tomonotonic input codes according to an embodiment of the presentdisclosure, while FIG. 8B is a graphic showing those monotonic inputcodes mapped against amplitude according in to an embodiment of thepresent disclosure;

FIG. 9A is a graphic illustrating an example of mapping input codes tomonotonic and linear input codes according to an embodiment of thepresent disclosure, while FIG. 9B is a graphic showing those monotonicand linear input codes mapped against amplitude according in to anembodiment of the present disclosure; and

FIG. 10A is a graphic of time step vs. input code when the ramp shapesof FIG. 5C are mapped to the input code by applying the relationshipillustrated by FIG. 9A according to an embodiment of the presentdisclosure, while FIG. 10B is a graphic of time step vs. amplitude ofthe modified input code according in to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described indetail with reference to the accompanying drawings. It should be notedthat the same elements will be designated by the same reference numeralsalthough they are shown in different drawings. In the followingdescription, specific details such as detailed configurations andcomponents are merely provided to assist the overall understanding ofthe embodiments of the present disclosure. Therefore, it should beapparent to those skilled in the art that various changes andmodifications of the embodiments described herein may be made withoutdeparting from the scope and spirit of the present disclosure. Inaddition, descriptions of well-known functions and constructions areomitted for clarity and conciseness. The terms described below are termsdefined in consideration of the functions in the present disclosure, andmay be different according to users, intentions of the users, orcustoms. Therefore, the definitions of the terms should be determinedbased on the contents throughout the specification.

The present disclosure may have various modifications and variousembodiments, among which embodiments are described below in detail withreference to the accompanying drawings. However, it should be understoodthat the present disclosure is not limited to the embodiments, butincludes all modifications, equivalents, and alternatives within thespirit and the scope of the present disclosure.

Although the terms including an ordinal number such as first, second,etc. may be used for describing various elements, the structuralelements are not restricted by the terms. The terms are only used todistinguish one element from another element. For example, withoutdeparting from the scope of the present disclosure, a first structuralelement may be referred to as a second structural element. Similarly,the second structural element may also be referred to as the firststructural element. As used herein, the term “and/or” includes any andall combinations of one or more associated items.

The terms used herein are merely used to describe various embodiments ofthe present disclosure but are not intended to limit the presentdisclosure. Singular forms are intended to include plural forms unlessthe context clearly indicates otherwise. In the present disclosure, itshould be understood that the terms “include” or “have” indicateexistence of a feature, a number, a step, an operation, a structuralelement, parts, or a combination thereof, and do not exclude theexistence or probability of addition of one or more other features,numerals, steps, operations, structural elements, parts, or combinationsthereof.

Unless defined differently, all terms used herein have the same meaningsas those understood by a person skilled in the art to which the presentdisclosure belongs. Terms such as those defined in a generally useddictionary are to be interpreted to have the same meanings as thecontextual meanings in the relevant field of art, and are not to beinterpreted to have ideal or excessively formal meanings unless clearlydefined in the present disclosure.

As discussed above, a dedicated 2G-PA front-end module for power-rampcontrol is the conventional solution to maintaining 2G transmissionstandards. However, a dedicated 2G-PA uses up many resources, such assilicon area, making it less practical and/or desirable in a broadbandmodem chip capable of multi-standard communication including 2G.

FIG. 1 is a diagram showing different aspects of a 2G slot transmission:the top is a simplified drawing of the waveform of the transmission(labelled “Output RF Signal”); the middle (labelled “Output RF SignalAmplitude”) shows the desired characteristics of the transmission,including A_(slot) the transmission slot amplitude; and the bottom(labelled “Output RF Signal Power (P_(out)) [in dB scale]”) shows theoutput RF signal power P_(out) in a logarithmic scale. Whentransmitting, the transceiver's P_(out) needs to be properly shaped forramp-up and ramp-down in order to ensure that the output signal meetsthe frequency-mask specifications as well the time-mask specificationsrelated to the output-power versus time profile. See, e.g., ETSI GSMRelease 1999, GSM 05.05 ver. 8.5.1 Release 1999, Annexes A and B.Nominally, the transceiver needs to be able to cover a 30 dBpower-control range for the maximum transmitted power P_(max) in thedata portion of the slot, although in practice, the range should belarger. Moreover, the P_(out) and A_(slot) can change, for a singlemobile terminal, from one transmission slot to its next allocatedtransmission slot.

Different solutions for multi-standard broadband modem chip design haverecently been suggested. See, e.g., Georgantas et. al. “A 13 mm 40 nmMultiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver”, ISSCC Dig. Tech.Papers, pp. 160-161, February 2015; and Strange et al., “AHSPA+/WCDMA/EDGE 40 nm Modem SoC with embedded RF transceiver supportingRX diversity”, 2014 IEEE Radio Frequency Integrated Circuits (RFIC)Symposium, pages 133-136, June 2014, which are both incorporated hereinby reference in their entirety.

The present application is also related to a digital power amplifier(DPA) based GMSK transmitter for the 2G mode which is embedded into a3G/4G I/Q modulator with minimum area penalty. See U.S. patentapplication Ser. No. 15/065,433, entitled “Apparatus for and Method ofProgrammable Matching Network for Multiple Signal Types” and filed onMar. 9, 2016 (hereinafter referred to as “the '433 application”), whichis incorporated herein by reference in its entirety. In the transceiver,a ramp generation block is implemented completely on chip and providesthe digital control signal for the DPA to ensure the 2G rampcharacteristics when transmitting a 2G slot. While the presentdisclosure is not limited in any way to the other application, the otherapplication may be referred to for ease of convenience concerning thegeneral environment some embodiments of the present disclosure could beimplemented in. Moreover, the present disclosure is not limited tomulti-standard modem chips, although highly useful for such chips, butmay be implemented in a 2G-only mobile terminal with a DPA. In anyembodiment, the ramp control of the present disclosure could beimplemented entirely on chip.

According to one embodiment, the present DPA provides ramp control byshaping the ramp per specified 2G requirements and avoidingnon-linearity and non-monotonicity.

FIG. 2A is a block diagram of DPA to which embodiments of the presentdisclosure are applied. As would be understood by one of ordinary skillin the art, FIG. 2A is a simplified block diagram, showing the pertinentdetails for the present disclosure, and a real-world implementationwould be much more complex, requiring, for example, more stages,components, input/output lines, and/or control lines, and would alsovary depending on the requirements of the particular implementation.

In FIG. 2A, DPA 210 has an n bit control input, a fixed-amplitudefrequency-phase modulated (or single tone) carrier signal 203 for input,and an amplified and/or otherwise shaped version of the input signal asoutput signal 205. The amplitude/shaping of output signal 205 is afunction of the n bit control input code, i.e., by changing the inputcontrol code the amplitude/shape of the output signal 205 can bechanged. In the 2G standard, the polar transmitter's output needs to beramped up at an assigned start, held at the desired amplitude, and thenramped down as shown in FIG. 1 above. The slot amplitude (A_(slot))needs to be set to a value between 0 and A_(max) depending on thesystem-specified requirement for that particular slot.

However, the relationship between the amplitude/shape of output signal205 and the digital input control code depends on the exactimplementation of the DPA.

When the DPA has a 6-bit control signal (n=6), the control signal valuesgo from 0 to 63 (=2⁶−1), which corresponds to a minimum amplitude of 0and a maximum amplitude A_(max) at the maximum code of 63, i.e., 63 isthe value of the input binary code which will cause the DPA to generatethe maximum amplitude. When the relationship between the amplitude/shapeof output signal and the digital input control code is monotonic andlinear, the amplitude/code graph of the control code going from 0 to 63looks like FIG. 2B.

However, in some DPAs, the relationship between the amplitude/shape ofthe DPA's output signal and its input control code is not monotonic andlinear for all input codes in all situations. Using the same 6-bitcontrol signal, an example of such a non-monotonic and non-linear outputsignal is shown in FIG. 2C. Such nonlinearity and/or non-monotonicitymight arise due to the particular way in which the DPA is designed. See,e.g., the '433 application. It may also arise from nonidealities in theDPA introduced during manufacturing or because of changing parameterslike temperature during operation.

In systems, apparatuses, and methods according to various embodiments ofthe present disclosure, a time-varying digital input DPA control code isgenerated that shapes the DPA's output amplitude A_(out) to avoidnon-monotonic and/or non-linear changes, regardless of the DPA'simplementation/construction—i.e., even with a DPA that usually generatessuch non-monotonic and/or non-linear changes when using normal digitalinput control code. Moreover, in systems, apparatuses, and methodsaccording to various embodiments of the present disclosure, the 2Gspecifications, such as the A_(out) level, the rate of rise/fall in aparticular ramp up/down, etc., are also met, even when using a DPA.Furthermore, ramp generation can be programmable, and theramp-generation block can be implemented entirely on-chip.

FIG. 3 is a flowchart of the general operations for amplitude-to-controlcode relationship model creation and ramp-up/ramp-down generation for aDPA according to an embodiment of the present disclosure. As would beunderstood by one of ordinary skill in the art, FIG. 3 is a simplifiedflowchart, its description below is a simplified overview forconvenience of explanation, and a real-world implementation would bemuch more complex, require more stages and/or components, and would alsovary depending on the requirements of the particular implementation.More detailed embodiments are described below.

At 305, the present process starts. This may happen, for example, thefirst time a broadband modem chip having a DPA according to anembodiment of the present disclosure is initiated, whether by themanufacturer or by a consumer after purchase.

At 310, the present system detects any input control codes which makethe DPA generate non-monotonic and/or non-linear outputs. At 315, thepresent system generates a monotonic and linear amplitude-to-controlinput code relationship profile for the DPA, which may be more or lessdifficult depending on whether non-monotonic and/or non-linear outputsare detected. At 320, the present system stores the monotonic and linearamplitude-to-control input code relationship profile for real-timeusage. The present system provides amplitude-to-control coderelationship model creation at 310-330 according to embodiments of thepresent disclosure.

At 325, the present system determines whether there is a modelre-calculation condition. If there is a model re-calculation condition,the process returns to 310-320 to generate a possibly newamplitude-to-control code relationship model. Examples of possible modelre-calculation conditions include, but are not limited to, operatingparameter changes, such as changes in temperature or power supplyvoltage to the DPA. Although 325 is shown in FIG. 3 as part of thereal-time operation of the DPA, 325 may not be a part of the real-timeoperation, but rather simply be triggered by the controller based on achange in temperature or power supply voltage.

At 330, the present system determines whether a TDMA slot is to begenerated. If so, then at 335, the present system retrieves a ramp shapefrom storage, in this case, a ramp-up shape, and adjusts the ramp shapefor the appropriate frequency and amplitude. At 340, the present systemshapes the frequency- and amplitude-adjusted ramp shape using theamplitude-to-control code relationship model created at 310-320 in orderto prevent any possible non-monotonicity and/or non-linearity. Next, at345, the present system ramps up the TX output power by clocking theshaped ramp shape into the DPA.

At the end of the ramp up phase, the present system transmits the dataportion at 350 as illustrated in FIG. 1. Once the data portiontransmission is complete, the present system retrieves the appropriateramp-down shape and adjusts it for frequency and amplitude at 355. At360, the present system shapes the ramp shape by using the monotonic andlinear amplitude-to-control input code relationship profile stored at330, before it is transmitted as the end of the slot at 365.

When the present system ramps down the TDMA slot at 365, the processreturns to 330 after the end of the ramp-down to wait for the generationof another TDMA slot. 330-365 constitute real-time ramp generationaccording to embodiments of the present disclosure.

In systems, apparatuses, and methods according to various embodiments ofthe present disclosure, any nonlinear and/or non-monotonic outputinherent in a DPA can be corrected. The actual amplitude at the outputof the DPA can be made to follow any shape with respect to time, even ifnormal input control code generates nonlinear/non-monotonic amplitudeoutput levels. Moreover, since a digital approach is being used,practically any nonlinear and/or non-monotonic amplitude output inherentin a DPA can be fixed. Depending on the modulation standard and itsrespective time mask(s), almost any ramp shape can be programmed.

Below, the real-time operation of the ramp generation block according toan embodiment of the present disclosure is described. As mentionedabove, the ramp-generation block can be programmable, implementedon-chip, ensure compliance with the 2G standard specifications, andavoid non-monotonic and/or non-linear changes in DPA output.

FIG. 4 is a block diagram of a DPA with a ramp generation blockaccording to an embodiment of the present disclosure. The implementationof the ramp generation block may take many forms, as would be understoodby one of ordinary skill in the art. For example, the ramp generationblock may be a digital block programmable using a hardware descriptionlanguage, such as, for example, Verilog or Very High Speed IntegratedCircuit (VHSIC) Hardware Description Language (VHDL), and synthesizedusing digital synthesis tools. FIGS. 5A-5C are amplitude graphsillustrating examples of how the ramp shape is generated and manipulatedin the ramp generation block. FIG. 6 is a flowchart of the real-timeoperation of a ramp generation block according to an embodiment of thepresent disclosure.

FIG. 4 has an n-bit DPA 410 of which the n-bit control signal isreceived from the ramp generation block, which includes a ramp shapestorage 420, a clock divider 430, a mixer 435, a multiplier 437, a rampshaper 440, and a relationship model storage 450. Where the examples ofamplitude graphs FIGS. 5A-5C would be generated within the rampgeneration block are marked in FIG. 4 as well.

When the ramp shape storage 420 receives a ramp start signal trigger(e.g., a SYNCH signal), the ramp shape storage 420 retrieves and outputsa stored customized ramp shape digital code, which may include anyarbitrary number of bits M. FIG. 5A is an example of a customized rampshape digital code Ramp_Shape as a raised cosine, where M=15 and thusthe ramp shape goes from 0 to 32,767 (=2¹⁵−1) over 56 time steps.

The “clock” (or frequency) of the stored customized ramp shape digitalcode is altered by mixing (435) the output of the clock divider 430 andthe stored customized ramp shape digital code. The clock divider 430receives a reference signal CLK, changes that reference signal CLK tothe desired clock for the ramp (by changing its divide ratio), andoutputs the desired clock to the mixer 435. FIG. 5B provides fourexamples of the ramp shape in FIG. 5A having its clock (frequency)changed. Specifically, from left to right, the first ramp is clocked at13 MHz, the second at 6.5 MHz, the third at 4.33 MHz, and the fourth at3.25 MHz.

The frequency-altered ramp shape, such as shown in FIG. 5B, ismultiplied (437) with the slot amplitude A_(slot) to be appropriatelyscaled to the appropriate slot level. FIG. 5C provides five examples ofthe amplitude of the ramp shape in FIG. 5A being scaled. On the righthand of each shape, the A_(slot)/A_(max) ratio is indicated.Specifically, from top to bottom, the first ramp is scaled atA_(slot)/A_(max)=1, the second at A_(slot)/A_(max)=0.8, the third atA_(slot)/A_(max)=0.6, the fourth at A_(slot)/A_(max)=0.4; and the fifthat A_(slot)/A_(max)=0.2.

Finally, the ramp shaper 440 receives the amplitude-adjusted andfrequency-adjusted ramp shape and appropriately shapes it to avoid thenon-linearity and non-monotonicity that may be inherent in DPA 410. Morespecifically, the ramp shape is adjusted according to a relationshipmodel retrieved from a relationship model storage 450. The generation ofthe stored relationship model is described below with reference to FIGS.7, 8A-8B, 9A-9B, and 10A-10B. As shown in FIG. 4, an example of theoutput of the ramp shaper 440 is illustrated by FIGS. 10A and 10B, whichare described further below.

As would be understood by one of ordinary skill in the art, FIG. 4 is asimplified diagram, the paragraphs above are an overview focusing on thedetails pertinent to the present disclosure, and a real-worldimplementation would be much more complex, require more stages and/orcomponents, and would also vary depending on the requirements of theparticular implementation.

FIG. 6 is a flowchart of the real-time operation of a ramp generationblock for DPA control according to an embodiment of the presentdisclosure.

The present system receives a synchronization signal that indicates thestart of a ramp-up or a ramp-down process. At 610, the present systemretrieves the ramp shape from storage and clocks the ramp shape to thedesired frequency. At 620, the present system scales the ramp shapeaccording the required maximum slot amplitude A_(slot) for thattransmission slot, which may be received from, e.g., the controller ofthe broadband modem chip. At 630, the present system retrieves therelationship model from storage and uses it to shape the ramp shape toavoid any possible non-linearities and/or non-monotonicities caused bythe specific DPA generating the slot signal. More specifically, thepresent system uses the stored monotonic/linear amplitude versus digitalinput code relationship generated for that DPA to create the final n-bitcontrol input for the DPA.

FIG. 7 is a flowchart of the one-time operation for generating arelationship model to be used by a ramp generation block according to anembodiment of the present disclosure. FIGS. 8A-8D are amplitude/codegraphs illustrating examples of how the input control code ismanipulated through the one-time operation according to an embodiment ofthe present disclosure.

At 710, the present system sweeps the input codes of the DPA in order todetermine the amplitude versus input control code relationship. In otherwords, each possible control input code is entered and the resultingoutput amplitudes are analyzed. At 715, the present system determineswhether the amplitude-to-control input code relationship is monotonic.If it is determined that the amplitude-to-control input coderelationship is not monotonic (NO at 715), the present system removesthe input control codes which produce the non-monotonic portions at 720.Using FIG. 3B as an example of a non-monotonic amplitude-to-controlinput code relationship, FIG. 8A shows the input codes (Input_Code) fromFIG. 2C mapped to a new set of input codes (Input_Code_Monotonic) wherethe non-monotonic codes are skipped.

After 720, or if all of the amplitude-to-control input coderelationships are monotonic (YES at 715), the process goes to 730. At730, the present system constructs monotonic amplitude-to-control inputcode relationships—i.e., if non-monoticity is found, modified inputcontrol codes replace the removed input codes so as to ensure monotonicamplitude-to-control input code relationships. Such a relationship isshown in FIG. 8B.

At 735, the present system determines whether the constructed monotonicamplitude-to-control input code relationships are linear, which canstill be the case when there is monotonicity. For example, when the newset of input codes Input_Code_Monotonic are mapped against amplitude inFIG. 8B, it is clear the resulting ramp is non-linear. Accordingly, thepresent system determines whether monotonic relationship is linear at735. If the monotonic relationship(s) is linear (735=YES), theconstructed monotonic and linear amplitude-to-control input coderelationships are stored as a model at 750. If the monotonicrelationship(s) is not linear (735=NO), the process continues at 740.

At 740, the monotonic amplitude-to-input control code relationshipsgenerated at 730 are adjusted for non-linearity, resulting in theconstruction of amplitude-to-input control code relationships which areboth monotonic and linear. This is done by inverting the nonlinearAmplitude versus Input_Code_Monotonic relationship as shown in theexample of FIG. 8B. FIG. 9A shows a new set of input codesInput_Code_Monotonic_Linear (mapped to the M-bit digital values of thestored ramp shape) constructed from adjusting the input codeInput_Code_Monotonic from FIGS. 8A-8B. Then, by mapping the Input_Codeto the Amplitude relationship of the DPA shown in FIG. 2C, theInput_Code_Monotonic_Linear to Amplitude relationship is both linear andmonotonic as shown in FIG. 9B.

At 750, the monotonic and linear amplitude-to-input control coderelationship model for the DPA is stored for use in real-time operation.For example, the model could be stored in Relationship Model Storage 450in FIG. 4.

In the description of FIG. 4, we noted that FIGS. 10A and 10B illustratean example of the output of Ramp Shaper 440, generated from themonotonic and linear amplitude-to-input control code relationship modelretrieved from Relationship Model Storage 450. In fact, FIGS. 10A and10B show the five examples of scaled ramp shapes illustrated in FIG. 5Cafter the application of the amplitude-to-input control coderelationship model illustrated by FIGS. 9A and 9B. More specifically,FIG. 10A is a graphic of the input code vs. time step, where the fivescaled ramp shapes in FIG. 5C have been mapped to the input code byapplying the Input_Code vs. Input_Code_Monotonic_Linear relationshipillustrated by FIG. 9A. Similarly, FIG. 10B is a graphic of the DPAamplitude versus time step.

Depending on the embodiment of the present disclosure, steps and/oroperations in accordance with the present disclosure may occur in adifferent order, or in parallel, or concurrently for different epochs,etc., in different embodiments, as would be understood by one ofordinary skill in the art. Similarly, as would be understood by one ofordinary skill in the art, FIGS. 3, 6, and 7 are simplifiedrepresentations of the actions performed, and real-world implementationsmay perform the actions in a different order or by different ways ormeans. Similarly, as simplified representations, FIGS. 3, 6, and 7 donot show other required actions and/or operations as these are known andunderstood by one of ordinary skill in the art and not pertinent and/orhelpful to the present description.

Depending on the embodiment of the present disclosure, some or all ofthe actions, steps, and/or operations may be implemented or otherwiseperformed, at least in part, on a mobile or portable device. A “mobiledevice” or “portable device” as used herein refers to any movableelectronic device having the capability of receiving wireless signals,including, but not limited to, multimedia players, communicationdevices, computing devices, navigating devices, etc. Thus,mobile/portable devices include, but are not limited to, laptops, tabletcomputers, Portable Digital Assistants (PDAs), mp3 players, handheldPCs, Instant Messaging Devices (IMD), cellular telephones, GlobalNavigational Satellite System (GNSS) receivers, watches, cameras or anysuch device which can be worn and/or carried on one's person. Theportable/mobile device may also be “User Equipment” or “UE” as that termis used in the 3^(rd) Generation Partnership Project (3GPP) Long TermEvolution (LTE)/LTE-Advanced (LTE-A) protocols, but is not in any waylimited by the 3GPP protocols.

Depending on the embodiment of the present disclosure, some or all ofthe steps and/or operations may be implemented or otherwise performed,at least in part, using one or more processors running instruction(s),program(s), interactive data structure(s), client and/or servercomponents, where such instruction(s), program(s), interactive datastructure(s), client and/or server components are stored in one or morenon-transitory computer-readable media. The one or more non-transitorycomputer-readable media may be instantiated in software, firmware,hardware, and/or any combination thereof. Moreover, the functionality ofany “block” or “module” discussed herein may be implemented in software,firmware, hardware, and/or any combination thereof.

As an example, various embodiments of the present disclosure could beimplemented as a part of a (possibly multi-standard) broadband and/orbaseband modem chip, as would be understood by one of ordinary skill inthe art, in view of the present disclosure.

The one or more non-transitory computer-readable media and/or means forimplementing/performing one or more operations/steps/modules ofembodiments of the present disclosure may include, without limitation,application-specific integrated circuits (“ASICs”), standard integratedcircuits, controllers executing appropriate instructions (includingmicrocontrollers and/or embedded controllers), field-programmable gatearrays (“FPGAs”), complex programmable logic devices (“CPLDs”), and thelike. Some or all of any system components and/or data structures mayalso be stored as contents (e.g., as executable or other non-transitorymachine-readable software instructions or structured data) on anon-transitory computer-readable medium (e.g., as a hard disk, a memory,a computer network or cellular wireless network or other datatransmission medium, or a portable media article to be read by anappropriate drive or via an appropriate connection, such as a DVD orflash memory device) so as to enable or configure the computer-readablemedium and/or one or more associated computing systems or devices toexecute or otherwise use or provide the contents to perform at leastsome of the described techniques. Some or all of any system componentsand data structures may also be stored as data signals on a variety ofnon-transitory computer-readable transmission mediums, from which theyare read and then transmitted, including across wireless-based andwired/cable-based mediums, and may take a variety of forms (e.g., aspart of a single or multiplexed analog signal, or as multiple discretedigital packets or frames). Such computer program products may also takeother forms in other embodiments. Accordingly, embodiments of thisdisclosure may be practiced in any computer system configuration.

Thus, the term “non-transitory computer-readable medium” as used hereinrefers to any medium that includes the actual performance of anoperation (such as hardware circuits), that includes programs and/orhigher-level instructions to be provided to one or more processors forperformance/implementation (such as instructions stored in anon-transitory memory), and/or that includes machine-level instructionsstored in, e.g., firmware or non-volatile memory. Non-transitorycomputer-readable media may take many forms, such as non-volatile andvolatile media, including but not limited to, a floppy disk, flexibledisk, hard disk, RAM, PROM, EPROM, FLASH-EPROM, EEPROM, any memory chipor cartridge, any magnetic tape, or any other magnetic medium from whicha computer instruction can be read; a CD-ROM, DVD, or any other opticalmedium from which a computer instruction can be read, or any othernon-transitory medium from which a computer instruction can be read.

While certain embodiments of the disclosure have been shown anddescribed herein it will be understood by those skilled in the art thatvarious changes in form and detail may be made without departing fromthe scope of the disclosure as defined by the appended claims.

What is claimed is:
 1. A method, comprising: detecting one or morecontrol input codes to a digital power amplifier (DPA) that generate anon-monotonic amplitude output; generating a monotonicamplitude-to-control input code relationship model for the DPA based onthe one or more control input codes; adjusting the monotonicamplitude-to-control input code relationship model to construct amonotonic and linear amplitude-to-control input code relationship model;and storing the monotonic and linear amplitude-to-control input coderelationship model, wherein, during ramp generation by the DPA, thestored monotonic and linear amplitude-to-control input code relationshipmodel is applied to a control code for one of a ramp-up and a ramp-downbefore the control input code is input to the DPA.
 2. The method ofclaim 1, wherein detecting one or more control input codes to the DPAthat generate non-monotonic amplitude output comprises: sweeping throughall of the control input codes to generate an amplitude-to-control inputcode relationship profile; and determining whether theamplitude-to-control input code relationship profile is monotonic. 3.The method of claim 2, wherein generating a monotonicamplitude-to-control input code relationship model for the DPA based onthe one or more control input codes comprises: isolating a control inputrange in which amplitude is non-monotonic based on determining that theamplitude-to-control input code relationship profile is non-monotonic.4. The method of claim 3, wherein isolating the control input range forwhich the amplitude is non-monotonic comprises: removing the controlinput range for which the amplitude is non-monotonic.
 5. The method ofclaim 3, wherein generating a monotonic amplitude-to-control input coderelationship model for the DPA based on the detecting step furthercomprises: modifying the control input range for which the amplitude isnon-monotonic to generate the monotonic amplitude-to-control input coderelationship model.
 6. The method of claim 1, wherein the steps ofdetecting, generating, adjusting, and storing are performed when abroadband chip comprising the DPA is initiated.
 7. The method of claim1, wherein the steps of detecting, generating, adjusting, and storingare performed when a model re-calculation condition is detected.
 8. Themethod of claim 7, wherein a model re-calculation condition comprises anoperating parameter change.
 9. The method of claim 1, wherein abroadband chip comprising the DPA is a multi-standard broadband chipcapable of 2G transmission for a polar transmitter.
 10. A method,comprising: if a time division multiple access (TDMA) slot is to begenerated by a digital power amplifier (DPA), retrieving control inputcode for a ramp-up shape from a ramp shape storage, where the controlinput code is for controlling an amplitude of the DPA; adjusting theretrieved control input code for frequency and amplitude; shaping thefrequency-adjusted and amplitude-adjusted control input code based on amonotonic and linear amplitude-to-control input code relationship model;and inputting the shaped control input code to the DPA to generate theramp-up shape, wherein the monotonic and linear amplitude-to-controlinput code relationship model is based on an amplitude-to-control inputcode relationship of the DPA.
 11. The method of claim 10, furthercomprising: generating a data portion of the TDMA slot after the ramp-upportion is generated.
 12. The method of claim 11, further comprising:retrieving control input code for a ramp-down shape from the ramp shapestorage; adjusting the retrieved control input code for frequency andamplitude; shaping the frequency-adjusted and amplitude-adjusted controlinput code based on a second monotonic and linear amplitude-to-controlinput code relationship model; and inputting the shaped control inputcode to the DPA to generate the ramp-down shape after the data portionof the TDMA is generated, wherein the second monotonic and linearamplitude-to-control input code relationship model was generated basedon the amplitude-to-control input code relationship of the DPA.
 13. Themethod of claim 10, wherein the monotonic and linearamplitude-to-control input code relationship model was previouslygenerated and stored in a relationship model storage.
 14. The method ofclaim 13, wherein the monotonic and linear amplitude-to-control inputcode relationship model was generated and stored by: detecting anycontrol input codes to the DPA which generate non-monotonic amplitudeoutput; generating a monotonic amplitude-to-control input coderelationship model for the DPA based on the detecting step; adjustingthe monotonic amplitude-to-control input code relationship model toconstruct a monotonic and linear amplitude-to-control input coderelationship model; and storing the monotonic and linearamplitude-to-control input code relationship model.
 15. The method ofclaim 14, wherein the steps of detecting, generating, adjusting, andstoring are performed when a model re-calculation condition is detected.16. A broadband modem chip, comprising: a digital power amplifier (DPA);at least one non-transitory computer-readable medium; and a processor,wherein, if a time division multiple access (TDMA) slot is to begenerated, the processor executes instructions stored on the at leastone non-transitory computer-readable medium, which, when executed, hasthe broadband modem chip perform at least the following steps:retrieving control input code for a ramp-up shape from a ramp shapestorage, where the control input code is for controlling an amplitude ofthe DPA; adjusting the retrieved control input code for frequency andamplitude; shaping the frequency-adjusted and amplitude-adjusted controlinput code based on a monotonic and linear amplitude-to-control inputcode relationship model; and inputting the shaped control input code tothe DPA to generate the ramp-up shape, wherein the monotonic and linearamplitude-to-control input code relationship model is based on anamplitude-to-control input code relationship of the DPA, and waspreviously generated and stored.
 17. The broadband modem chip of claim16, wherein, when the broadband modem chip was initiated, the monotonicand linear amplitude-to-control input code relationship model wasgenerated and stored by: detecting any control input codes to the DPAwhich generate non-monotonic amplitude output; generating a monotonicamplitude-to-control input code relationship model for the DPA based onthe detecting step; adjusting the monotonic amplitude-to-control inputcode relationship model to construct a monotonic and linearamplitude-to-control input code relationship model; and storing themonotonic and linear amplitude-to-control input code relationship model.18. The broadband modem chip of claim 16, wherein, when a modelre-calculation condition is detected, a new monotonic and linearamplitude-to-control input code relationship model is generated andstored by: detecting any control input codes to the DPA which generatenon-monotonic amplitude output; generating a monotonicamplitude-to-control input code relationship model for the DPA based onthe detecting step; adjusting the monotonic amplitude-to-control inputcode relationship model to construct a monotonic and linearamplitude-to-control input code relationship model; and storing themonotonic and linear amplitude-to-control input code relationship model.19. The broadband modem chip of claim 18, wherein a model re-calculationcondition comprises an operating parameter change.
 20. The broadbandmodem chip of claim 16, wherein the broadband modem chip is amulti-standard broadband chip capable of 2G transmission for a polartransmitter.